1. Field of the Invention
The present invention generally relates to controlling access to dynamic random access memory (DRAM) and, more specifically, to an approach to virtual bank management in dynamic random access memory (DRAM) controllers.
2. Description of the Related Art
Dynamic random access memory (DRAM) is employed in a variety of computing devices such as personal computers, laptops, gaming consoles, and graphics processing units due to the relatively high density and low power requirements of DRAM memory as compared to other alternatives. One difficulty in using DRAM memory, however, is that DRAM memory typically is subject to a variety of timing constraints in order to ensure proper operation and retention of data stored in DRAM. For example, memory cells within DRAM are periodically refreshed. Failure to timely refresh DRAM memory results in loss of data. As a result, systems using DRAM include one or more DRAM bank managers to refresh DRAM memory cells and meet other timing requirements of DRAM. In such implementations, the main processing unit is not burdened with managing these DRAM timing constraints.
DRAM performance may be improved by sub-dividing the DRAM into multiple banks of memory, where each bank includes a portion of the memory cells within a DRAM module. In such configurations, banks of DRAM may accessed in an interleaved fashion, where an access to one bank of memory occurs simultaneously with an access to a second bank of memory, but the memory accesses are offset in time with respect to each other. Typically, each DRAM bank is managed by a separate bank manager that manages the bank-specific timing parameters for the corresponding DRAM bank. One disadvantage of this approach is that a greater quantity of banks in a DRAM module results in a correspondingly greater quantity of bank mangers in the DRAM controller. Further, as DRAM architectures have evolved, the number of banks in the DRAM memory has increased, and the number of bank managers in a typical DRAM controller have proportionately increased as well. As a result, a significant portion of the surface area on a DRAM controller integrated circuit is dedicated to bank managers.
In addition to these problems, DRAM access patterns in certain applications are such that only a small portion of the DRAM banks are actively read or written at any given time. During such times, the bank managers corresponding to the active banks of DRAM memory are utilized, but the remaining bank managers are idle. Consequently, a relatively large area within a DRAM controller integrated circuit is devoted to a function that is idle for significant portions of time.
As the foregoing illustrates, what is needed in the art is a technique that more efficiently utilizes bank managers within a DRAM controller.